Delay in regulators of time discrete single-ended synchronization

Mutual single-ended synchronization of digital telecommunication networks is subject to two different types of delay. One type is the delay in transmission lines and the other type is the delay in regulators. Here, the regulator delay is investigated with two time discrete linear regulators: proportional (P) and proportional plus integrating (PI) regulators. Depending on the realization of the regulator circuit the delay of frequency correction may amount to a substantial part of the sampling interval. The effect of the regulator delay on both P and PI regulators is the same as of an added derivative term. The gain of this derivative term equals the negative product of the delay time and the original proportional gain. The stability domain for the regulator delay depends on both the regulator gains and on the connectivity of a network. But, there are suitable settings of regulator gains for which any network will remain stable for a regulator delay of up to the entire sampling interval. One suitable setting is, for example: proportional gain less than 50% and integrating gain less than 0.5% of their respective maximum stable ranges. The dependence of the regulator delay on the network connectivity is not explicitly derived, but it has been established that networks with less connections per node tolerate longer delays than fully interconnected ones.