• DocumentCode
    3045432
  • Title

    Theory and practice of sequential machine testing and testability

  • Author

    Pomeranz, Irith ; Reddy, Sudhakar M. ; Patel, Janak H.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
  • fYear
    1993
  • fDate
    22-24 June 1993
  • Firstpage
    330
  • Lastpage
    337
  • Abstract
    Undetectable and redundant faults in synchronous sequential circuits have recently received wide attention. Previous classifications of detectable, undetectable and redundant faults in such circuits assume certain restrictions regarding the operation of the circuit-under-test. In this work, no restrictions are imposed, and faults are classified on the basis of the existence (or lack) of an input/output experiment that distinguishes the fault free and faulty circuits. It is shown that faults that were previously considered redundant are detectable according to the new definitions (detectable in a probabilistic sense). The practical usefulness of the fault classification presented is discussed.
  • Keywords
    logic testing; fault classification; fault-free circuits; faulty circuits; redundant faults; sequential machine testability; sequential machine testing; synchronous sequential circuits; undetectable faults; Circuit faults; Circuit testing; Cities and towns; Combinational circuits; Contracts; Electrical fault detection; Fault detection; Manufacturing processes; Sequential analysis; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Fault-Tolerant Computing, 1993. FTCS-23. Digest of Papers., The Twenty-Third International Symposium on
  • Conference_Location
    Toulouse, France
  • ISSN
    0731-3071
  • Print_ISBN
    0-8186-3680-7
  • Type

    conf

  • DOI
    10.1109/FTCS.1993.627336
  • Filename
    627336