Title :
A dynamic comparator with analog offset calibration for biomedical SAR ADC applications
Author :
Herath, M.M.J. ; Chan, P.K.
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
A new ultra-low voltage and power digital comparator using analog offset calibration technique is presented in this paper. The comparator´s input transistors are working in subthreshold region for the entire input range and is used as a zero crossing detector for the analog offset calibration technique. Realized using GLOBALFOUNDRIES 0.18μm CMOS process technology, at the voltage supply of 0.7V and 1MHz clock frequency, the standalone comparator dissipates 153nW but increasing to 494nW with calibration function. For voltage supply down to 0.4V and 20 kHz clock, the single comparator dissipates only 8.054nW. The calibration circuit is capable of reducing a 20mV of input-referred dc offset down to 655.3μV, making it suitable for 10-bit biomedical SAR ADC applications.
Keywords :
CMOS integrated circuits; analogue-digital conversion; biomedical electronics; calibration; comparators (circuits); low-power electronics; prosthetics; transistors; analog offset calibration technique; biomedical SAR ADC applications; comparator input transistors; dynamic comparator; frequency 1 MHz; frequency 20 kHz; global foundries CMOS process technology; low-power digital comparator; low-power successive approximation ADC design; power 153 nW; power 8.054 nW; size 0.18 mum; ultra-low voltage comparator; voltage 0.4 V; voltage 0.7 V; voltage 20 mV to 655.3 muV; word length 10 bit; zero crossing detector; Calibration; Clocks; Detectors; Logic gates; Power demand; Random access memory; Transistors;
Conference_Titel :
Integrated Circuits (ISIC), 2011 13th International Symposium on
Conference_Location :
Singapore
Print_ISBN :
978-1-61284-863-1
DOI :
10.1109/ISICir.2011.6131958