A 3bit 36GS/s flash ADC in 65nm low power CMOS technology

A 36GS/s 3bit flash ADC with a large analog input bandwidth is realized in a 65 nm CMOS technology. By employing a fourfold parallelization a high sampling rate is achieved, while a large input bandwidth is maintained. The measured effective resolution is about 2 bit up to 20GHz input signal frequency at a sampling rate of 36GS/s. The power consumption of the ADC core is 2.6W, the core area is 0.16 mm². The ADC is intended for the cost-effective integration with an equalizer circuit on a single CMOS chip.