CMOS Integrated Stress Mapping Chips with 32 N-Type or P-Type Piezoresistive Field Effect Transistors

This paper reports a novel generation of CMOS stress mapping chips comprising 32 square field effect transistors (FET) with four source/drain contacts (piezo-FETs) exploiting the shear piezoresistive effect in n-type (NMOS) or p-type (PMOS) inversion layers. The sensor chips with a total die area of 2.5 times 2 mm² are integrated with analog circuitry and digital logic. When exposed to homogenous shear or normal stress, all 32 integrated stress sensors show a linear response in excellent agreement with theoretical predictions and exhibit identical stress sensitivities. Piezo-FETs fabricated as separate devices are characterized with respect to stress sensitivity, intrinsic offset, and noise behavior. Stress sensitivities are enhanced by incorporating a central hole into the piezo-FETs. Sensitivities of -448 muV/(V MPa) and 477 muV/(V MPa) were measured for NMOS and PMOS devices, respectively.