Design of support vector machine circuit for real-time classification

This paper describes the design of support vector machine circuit for real-time classification. By unifying the algorithms and architectures of linear and non-linear SVM classifications, the proposed circuit can support both linear and non-linear classifications. The circuit size is minimized by sharing most of the resources required in the computation for both classification types. The sliding window size of 64×64 or 48×96 with 18 window strides is applied to the proposed circuit for efficient classification. Since the proposed circuit can process up to 31 640×480 image frames per second, it is sufficient to be used for real-time classification. The synthesized circuit using 65nm standard cell library consists of 654,435 gates and its maximum operating frequency is 178MHz.