Algorithmic synthesis of high level tests for data path designs

Algorithmic techniques are proposed to synthesize design verification programs for high level data path designs that target design defects as well as manufacturing defects. Some categories of design defects are identified. A methodology, based on localized checking experiments, is proposed to synthesize state machine controllers in data path designs that enhance manufacturing defect coverage using design verification programs. Some example designs are considered that demonstrate the effectiveness of the proposed techniques. A heuristic to generate universal tests for manufacturing defect coverage is proposed. This heuristic has been successfully applied for real design implementations of counters, adders, and comparators.