A PLL with a VCO of improved PVT tolerance

VCO has been the central block of a PLL used for on-chip clock generation. Due to the variation in process, voltage and temperature, the ratio of the VCO frequency at the fastest condition to the slowest condition could be a factor of 2~3. Also, significant variation of VCO gain is expected. For the same target VCO frequency, the loop bandwidth and stability could thus vary greatly due to the variation in the VCO gain. The designer needs to design the bandwidth and stability of the PLL so that it can function properly under all different PVT conditions. For example, the bandwidth is selected based on the worst-case condition, i.e. the fastest condition, trading off for less optimal bandwidths at other conditions. In this paper, the design of a compensation scheme to improve the PVT tolerance of a VCO is described. A four-stage differential ring oscillator with voltage regulation is employed to achieve the voltage tolerance. Depending on the process corner and temperature, the proposed compensation scheme works by changing the control current, thereby maintaining the desired frequency. The variation of frequency at 25°C is within ± 0.6% for the tuning voltage range from 0.4V to 1.5V comparing the fastest to slowest conditions. The variation of frequency at each control voltage point is within ±3.9% across a temperature range of -40°C to 125°C. A charge pump PLL is implemented with this VCO, demonstrating desired advantages as compared to a conventional VCO without compensation.