Title :
A Flipped Voltage Follower based low-dropout regulator with composite power transistor
Author :
Chong, S.S. ; Chan, P.K.
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
This paper presents an improved design for the low-dropout regulator (LDO) based on the Flipped Voltage Follower (FVF) structure. A FVF based LDO regulator with composite power transistor (CPT) is proposed. It reduces the minimum biasing current requirement of the power transistor in Single-Transistor-Control (STC) LDO regulator whilst enhancing the loop gain as well as bandwidth performance. The proposed LDO regulator has been validated using GLOBALFOUNDRIES 0.18-μm CMOS process. Using the FVF STC structure as the benchmark, the simulation results have shown that the proposed CPT LDO regulator has a better load transient and accuracy than that of the STC and Buffered Flipped Voltage Follower (BFVF) counterpart whilst maintaining low voltage operation.
Keywords :
CMOS analogue integrated circuits; low-power electronics; operational amplifiers; power transistors; BFVF; CMOS process; CPT; FVF based LDO regulator; STC LDO regulator; buffered flipped voltage follower; composite power transistor; load transient; low-dropout regulator; minimum biasing current; single-transistor-control LDO regulator; size 0.18 mum; Bandwidth; Logic gates; Power transistors; Regulators; Transient analysis; Transistors; Voltage control;
Conference_Titel :
Integrated Circuits (ISIC), 2011 13th International Symposium on
Conference_Location :
Singapore
Print_ISBN :
978-1-61284-863-1
DOI :
10.1109/ISICir.2011.6131999
