DocumentCode :
3046362
Title :
The dynamic rollback problem in concurrent event-driven fault simulation
Author :
Farinetti, Laura ; Montessoro, Pier Luca
Author_Institution :
Dipt. di Autom. e Inf., Politecnico di Torino, Italy
fYear :
1997
fDate :
27 Apr-1 May 1997
Firstpage :
282
Lastpage :
287
Abstract :
Both simulation for design verification and fault simulation in conjunction with automatic test pattern generation (ATPG) would benefit from forward and backward shifting of the simulation time. Except in some particular cases, however this has so far been only allowed through explicit save/restore commands issued by the user. The paper presents a general technique that makes a “run for T” command possible, where T can be any positive or negative time value. A major feature is that the user can set she maximum allowable overhead. Its generality allows its implementation in simulators for design verification and fault simulators, for both synchronous and asynchronous circuits, with either zero-delay or accurate delay models
Keywords :
delays; fault diagnosis; formal verification; logic CAD; logic testing; ATPG; asynchronous circuits; automatic test pattern generation; concurrent event-driven fault simulation; delay models; design verification; dynamic rollback problem; synchronous circuits; zero-delay; Asynchronous circuits; Automatic control; Automatic test pattern generation; Circuit faults; Circuit simulation; Control system synthesis; Delay; Discrete event simulation; Hardware design languages; Performance analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
ISSN :
1093-0167
Print_ISBN :
0-8186-7810-0
Type :
conf
DOI :
10.1109/VTEST.1997.600289
Filename :
600289
Link To Document :
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