DocumentCode :
3046452
Title :
Planarization process using a multi-coating of spin-on-glass
Author :
Kojima, H. ; Iwamori, T. ; Sakata, Y. ; Yamashita, T. ; Yatsuda, Y.
Author_Institution :
Fuji Xerox Co. Ltd., Kanagawa, Japan
fYear :
1988
fDate :
13-14 June 1988
Firstpage :
390
Lastpage :
396
Abstract :
A double-level metallization process using a multi-coating of silanol-type spin-on glass (SOG) has been developed. For finer patterns, it is difficult to fill the narrow grooves between the first Al lines and therefore the interlevel dielectric layer cannot be sufficiently planarized in the conventional single-coating process. A multi-coating technique with a modified three-step curing process was developed to solve this problem. The multi-coating process exhibited good planarization when checked by observing a cross-sectional view of the devices. The open and short yields of the second Al lines were also very good, and the resistance of the second Al line decreased to about 80% at quadruple coating compared with a single coating. No failures appeared in the pressure-cooking test and temperature cycling test.<>
Keywords :
aluminium; metallisation; semiconductor technology; Al lines; double-level metallization; interlevel dielectric layer; multi-coating; planarization; pressure-cooking test; spin-on-glass; temperature cycling test; three-step curing; Coatings; Curing; Dielectrics; Planarization; Plasma applications; Sputter etching; Surface resistance; Surface topography; Temperature; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1988. Proceedings., Fifth International IEEE
Conference_Location :
Santa Clara, CA, USA
Type :
conf
DOI :
10.1109/VMIC.1988.14217
Filename :
14217
Link To Document :
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