DocumentCode :
3046559
Title :
Architecture for a digital programmable image processing element
Author :
White, Stanley A.
Author_Institution :
Rockwell International, Anaheim, California
Volume :
6
fYear :
1981
fDate :
29677
Firstpage :
658
Lastpage :
661
Abstract :
A very high speed integrated circuit is required to perform a 3-pixel-by-3-pixel sliding window convolution over an image. To perform this on real-time video requires on the order of 
or 71 × 106multiplies/sec. A device has been designed to perform 90 × 106multiply-accumulate operations/sec. using 8-bit input words and providing full precision output. Since the device can perform general vector multiplication, it is therefore useful for general digital filtering. Sets of devices may be used to increase accuracy or to chain together to form high-order FIR filters, This paper describes the algorithms and architecture used within the device.
or 71 × 106multiplies/sec. A device has been designed to perform 90 × 106multiply-accumulate operations/sec. using 8-bit input words and providing full precision output. Since the device can perform general vector multiplication, it is therefore useful for general digital filtering. Sets of devices may be used to increase accuracy or to chain together to form high-order FIR filters, This paper describes the algorithms and architecture used within the device.Keywords :
Clocks; Convolution; Digital filters; Filtering; Finite impulse response filter; High performance computing; Image processing; Pins; Very high speed integrated circuits; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '81.
Type :
conf
DOI :
10.1109/ICASSP.1981.1171243
Filename :
1171243
Link To Document :
