Generation of representative traces for performance evaluation of computer architectures

Trace-driven simulation is common technique to accurately estimate the performance of computer systems. Accuracy of the estimated performance greatly depends on the traces as well as the system model itself. The trace based performance evaluation, however, suffers from the high cost of trace generation and execution. This has, provided the necessary impetus towards the development of accurate trace sampling methodologies. In this paper, we have presented a new methodology for generating and validating representative reduced traces. Experimental results show effectiveness and usefulness of the proposed technique