VIS-based native video processing on UltraSPARC

Author

Mou, Z. J Alex ; Rice, Daniel S. ; Ding, Wei

Author_Institution

Imaging & video Group, Sun Microsystems Comput. Co., Mountain View, CA, USA

Volume

1

fYear

1996

fDate

16-19 Sep 1996

Firstpage

153

Abstract

The UltraSPARC CPU powers Sun Microsystems´ latest workstations. It is the first major CPU to implement a comprehensive set of instructions aimed at high performance digital image and video processing-the Visual Instruction Set, or VIS. This is equivalent to the integration of a parallel DSP core into the CPU, rather than a coprocessor approach. We describe VIS and its application to the implementation of video processing algorithms in an H.261 codec

Keywords

discrete cosine transforms; instruction sets; parallel algorithms; parallel architectures; transform coding; video codecs; video coding; visual programming; workstations; DCT; Discrete cosine transform; H.261 codec; SIMD; Sun Microsystems workstations; UltraSPARC CPU; VIS based native video processing; Visual Instruction Set; convolution; digital image processing; digital video processing; motion estimation; parallel DSP core; video processing algorithms; Acceleration; Application software; Arithmetic; Central Processing Unit; Coprocessors; Hardware; Sun; Video codecs; Videoconference; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Processing, 1996. Proceedings., International Conference on

Conference_Location

Lausanne

Print_ISBN

0-7803-3259-8

Type

conf

DOI

10.1109/ICIP.1996.560625

Filename

560625