Prefetching scheme for image processing on shared memory multiprocessors

We propose a prefetching scheme for image processing which fully exploits regular memory references, and hides or reduces latencies from memory to cache in shared memory multiprocessors. Since the image processing applications usually require quite huge memory references, it is obvious that the memory latencies dominate the overall execution time. Though software-controlled prefetching can be also an alternative to alleviate such latency impact, it usually suffers from large overheads due to the prefetch instructions themselves which would offset the benefit obtained from prefetching. This paper proposes a new software-controlled prefetching scheme that prefetches multiple blocks using a prefetch instruction. It is designed in consideration of very regular memory references which is intrinsic to most image processing applications. Our scheme reduces almost all the memory stall time for loads and significantly the overall execution time. Simulation applications have shown a reduction in the execution time by 10-21% compared to the original methods without prefetching