Efficient encoding of quasi-cyclic low-density parity-check codes

This paper presents methods for efficient encoding of quasi-cyclic LDPC codes. Based on these methods, encoding of quasi-cyclic LDPC codes can be implemented using simple shift-registers with complexity linearly proportional to the number of parity-check bits of a code for serial encoding and to the length of a code for parallel encoding. Various encoding circuits are devised and they provide a range of trade-offs between encoding complexity and speed.