DocumentCode :
3047033
Title :
Design And Testing Of SEU/ SEL Immune Memory And Logic Circuits In A Commercial Cmos Process
Author :
Wiseman, Don ; Canaris, John ; Whitaker, Sterling ; Venbrux, Jack ; Cameron, Kelly ; Arave, Kari ; Arave, Larry ; Liu, M. Norley ; Liu, Kathy
Author_Institution :
University of New Mexico
fYear :
1993
fDate :
34171
Firstpage :
51
Lastpage :
55
Keywords :
CMOS logic circuits; CMOS process; Circuit testing; Logic circuits; Logic devices; Logic testing; Master-slave; Radiation hardening; Shift registers; Single event upset;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radiation Effects Data Workshop, 1993., IEEE
Print_ISBN :
0-7803-1906-0
Type :
conf
DOI :
10.1109/REDW.1993.700568
Filename :
700568
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3047033
