• DocumentCode
    3047977
  • Title

    FloRA: Coarse-grained reconfigurable architecture with floating-point operation capability

  • Author

    Lee, Dongwook ; Jo, Manhwee ; Han, Kyuseung ; Choi, Kiyoung

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea
  • fYear
    2009
  • fDate
    9-11 Dec. 2009
  • Firstpage
    376
  • Lastpage
    379
  • Abstract
    This paper demonstrates a chip implementation of coarse-grained reconfigurable architecture named FloRA. Two-dimensional array of integer processing elements in the FloRA is configured in run-time to perform integer functions as well as floating-point functions. FloRA is implemented in Dongbu HiTek 130 nm process and evaluate by running applications including physics engine and JPEG decoder.
  • Keywords
    CMOS integrated circuits; reconfigurable architectures; CMOS technology; Dongbu HiTek process; FloRA; JPEG decoder; coarse-grained reconfigurable architecture; floating-point operation capability; floating-point reconfigurable array; integer processing elements; size 130 nm; two-dimensional array; Buffer storage; Decoding; Engines; Kernel; Physics; Process control; Reconfigurable architectures; Reduced instruction set computing; Registers; Runtime;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field-Programmable Technology, 2009. FPT 2009. International Conference on
  • Conference_Location
    Sydney, NSW
  • Print_ISBN
    978-1-4244-4375-8
  • Electronic_ISBN
    978-1-4244-4377-2
  • Type

    conf

  • DOI
    10.1109/FPT.2009.5377609
  • Filename
    5377609
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3047977