Generating dynamically scheduled memory address traces

It is common practice to study the performance of a computer memory hierarchy design via trace-driven simulation. The validity of such studies is dependent on the accuracy of the memory address trace that is used to drive the simulations. To study the performance of a memory hierarchy for a multiprogrammed computer system, the accuracy of the trace is defined by the length, in terms of the number of memory addresses, of the trace segments that comprise each process trace and the method used to interleave process trace segments. This paper reviews methods that have been used to generate memory address traces for use in simulating memory hierarchy designs. More importantly, it presents a new and more accurate method of generating these traces. Given a set of annotated uniprogram memory address traces (UMATs), which are associated with the processes that comprise the workload being studied, a specification of the design of the processor cycle time, memory hierarchy design, system call service times, and scheduling policy, this method dynamically generates a trace at simulation time by defining the correct trace segment interleaving via the correct process scheduling. One set of UMATs can be used to generate accurate traces for a variety of configurations of simulated systems