Title :
Gate Work Function and Contact Engineering in Nanoscale Vertical Pillar Transistor for DRAM Cell Transistors
Author :
Jeong, Min-Kyu ; Park, Ki-Heung ; Kim, Young Min ; Lee, Jong-Ho
Author_Institution :
Kyungpook Nat. Univ., Deagu
Abstract :
In this work, p+/n+ gate structure is applied to vertical pillar transistor (VPT) for DRAM cell transistor to reduce gate induced drain leakage (GIDL) current. The VPT performance with contact structure and source/drain (S/D) geometry connected to cell capacitor node was investigated.
Keywords :
DRAM chips; MOS capacitors; MOSFET; leakage currents; nanocontacts; nanoelectronics; work function; DRAM cell transistors; MOSFET; VPT; capacitor node; contact engineering; gate induced drain leakage; gate induced drain leakage current; gate work function; nanoscale vertical pillar transistor; p+-n+ gate structure; source-drain geometry; Capacitors; Contact resistance; Degradation; Geometry; Immune system; MOS devices; MOSFETs; Random access memory; Solids; Writing;
Conference_Titel :
Microprocesses and Nanotechnology, 2007 Digest of papers
Conference_Location :
Kyoto
Print_ISBN :
978-4-9902472-4-9
DOI :
10.1109/IMNC.2007.4456130
