Design and synthesis for testability of synchronous sequential circuits based on strong-connectivity

The importance of strong-connectivity of the state diagram of a circuit in ensuring testability, specifically, in ensuring that no partially detectable faults exist, is shown. Partially detectable faults are irredundant faults that can be detected only if the circuit-under-test starts from specific initial states. They complicate the test generation and test application processes, and are therefore undesirable. Two methods are proposed to ensure that no partially detectable faults exist, through design for testability and through resynthesis of the circuit. Experimental results are presented for both methods. The incorporation of a redundancy removal procedure into the process of eliminating partially detectable faults, to make a circuit fully testable, is also discussed.