Control of multiprocessor SPS-1000 configurations using principles of data-flow architecture

The Data-Flow form of processor architecture has been investigated extensively in the context of general purpose computers and its applicability to signal processing has been suggested, but instances of the application of these principles are rare. In contrast to the conventional Von Neumann architecture in which a single program is executed in a sequence prescribed by the programmer and even to processors with multiple-instruction streams, a data-flow processor has no specified instruction ordering. Instead, instructions act on specific operands and the sequence of instruction execution is determined at run-time by the order in which the various operands become available. This technique of data-driven dynamic scheduling extends naturally to multiprocessors and is the basis for control of multiprocessor configurations of the SPS-1000 high-speed FFT processor.