Title :
A VLSI architecture for discrete wavelet transform
Author :
Chen, Xuyun ; Zhou, Ting ; Zhang, Qianling ; Li, Wei ; Min, Hao
Author_Institution :
ASIC & Syst. State-Key Lab., Fudan Univ., Shanghai, China
Abstract :
The discrete wavelet transform (DWT) has received considerable attention in the context of image processing due to its temporal and frequency characteristics. A specific VLSI architecture for the forward/inverse DWT is presented. The characteristics of the structure and coefficients are utilized to reduce the circuit area. In addition, the Booth algorithm and balanced pipelines have been adopted which result in a high throughput at 2 outputs per clock and 5 clocks´ pipeline latency. This design described and verified by the VHDL is synthesized by the Synopsys synthesizer. The synthesis results show that the gate-level circuit contains 5058 gates and the throughput can reach 110 M points/s when LSI 10 K CMOS technology is used
Keywords :
CMOS digital integrated circuits; VLSI; digital signal processing chips; image coding; image resolution; inverse problems; pipeline arithmetic; transform coding; wavelet transforms; Booth algorithm; CMOS technology; LSI; Synopsys synthesizer; VHDL; VLSI architecture; balanced pipelines; circuit area reduction; discrete wavelet transform; forward/inverse DWT; frequency characteristics; gate-level circuit; high throughput; image coding; image processing; multiresolution analysis; pipeline latency; temporal characteristics; wavelet coefficients; CMOS technology; Circuit synthesis; Clocks; Delay; Discrete wavelet transforms; Frequency; Image processing; Pipelines; Throughput; Very large scale integration;
Conference_Titel :
Image Processing, 1996. Proceedings., International Conference on
Conference_Location :
Lausanne
Print_ISBN :
0-7803-3259-8
DOI :
10.1109/ICIP.1996.561075
