A synthesis tool for fault-tolerant finite state machines

The authors present a synthesis tool for FSMs tolerating a single fault in the sequencing logic (next state logic or state register). Two architectures based on the use of SEC codes can be automatically implemented using this tool. The fault-tolerant FSMs can be generated either from a state transition graph specified, for example, in Kiss format or in VHDL, or for designs synthesized, using a control-driven approach, from higher level (e.g., RTL) specifications. The two FSM architectures are briefly presented. Then, the related synthesis flows, the main specific procedures and the synthesis options are described. Results obtained on international benchmark implementations are discussed.