Memory performance model for loops and kernels on Power3 processors

Summary form only given. A performance model for loops and kernels limited by memory access is developed that is applicable to Power3 processors. The output of the model is the time delay arising from cache and TLB misses. The input variables are the miss rates of each cache and the TLB, while the model parameters are the miss penalties of each cache and the TLB. Load misses are treated separately from store misses and typically have smaller penalties because of prefetching. The parameters have been obtained by fits to data from simple test loops measured with a hardware performance monitor. Results are presented for two types of Power3 processor running in serial as well as for one of the processor types running in parallel. For codes limited by store misses, the model fits the data very well. For codes limited by load misses, the model shows greater variability relative to the data, presumably because of the limited treatment of prefetching.