Title :
Design of a color reproduction neural network chip with on-chip learning capability
Author :
Ker, Jar-Shone ; Kuo, Yau-Hwang ; Liu, Bin-Da
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
The process of eliminating color errors from the gamut mismatch, resolution conversion, quantization and non-linearity between scanner and printer is an essential issue of color reproduction. To efficiently calibrate the non-linear color distortion characteristic between color scanner and printer and to enhance the reproduction quality of color documents, we develop a hardware processing module, which realizes the operation of a higher order CMAC neural network model with linear systolic array architecture, to on-line calibrate the color during the reproducing session. This mapping scheme exhibits fast computation speed in evaluating the output responses of higher-order CMAC model
Keywords :
CMOS digital integrated circuits; calibration; cerebellar model arithmetic computers; digital signal processing chips; document image processing; error analysis; image colour analysis; image enhancement; integrated circuit layout; learning (artificial intelligence); neural chips; optical noise; systolic arrays; color document; color errors; color reproduction neural network chip; computation speed; enhancement; gamut mismatch; hardware processing module; higher order CMAC neural network model; linear systolic array architecture; nonlinear color distortion characteristic; nonlinearity; on-chip learning capability; on-line calibration; output responses; printer; quantization; reproduction quality; resolution conversion; scanner; Brain modeling; Color; Convergence; Network-on-a-chip; Neural network hardware; Neural networks; Nonlinear distortion; Printers; Spline; Systolic arrays;
Conference_Titel :
Image Processing, 1996. Proceedings., International Conference on
Conference_Location :
Lausanne
Print_ISBN :
0-7803-3259-8
DOI :
10.1109/ICIP.1996.561081
