Title :
An on-line testable UART implemented using IFIS
Author :
Yeandel, J. ; Thulborn, D. ; Jones, S.
Author_Institution :
Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK
fDate :
27 Apr-1 May 1997
Abstract :
This paper presents the design of a complex integrated circuit realised through a novel on-line test methodology. The circuit and its exact conventional equivalent both have been realised in FPGA technology. As such it represents one of the more complex designs realised to date using on-line test approaches. The approach used IFIS (If it Fails It Stops) incorporates dual-rail coding of individual data and a handshaking protocol, which substantially simplifies the detection of failure. Details of the IFIS methodology are given. The IFIS and conventional re-design of a commercial UART are reported, focusing on methodological issues as well as size and speed. Output traces are shown for the IFIS UART on FPGA operating under fault-free conditions and with deliberate failures injected
Keywords :
VLSI; automatic testing; data communication equipment; field programmable gate arrays; integrated circuit testing; logic testing; telecommunication equipment testing; FPGA technology; IFIS methodology; complex integrated circuit; dual-rail coding; failure detection; handshaking protocol; online testable UART; Circuit faults; Circuit testing; Costs; Design methodology; Electronic equipment testing; Encoding; Field programmable gate arrays; Integrated circuit technology; Integrated circuit testing; Protocols;
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-7810-0
DOI :
10.1109/VTEST.1997.600301
