Title :
Towards a balanced ternary FPGA
Author_Institution :
Electr. & Comput. Eng., RMIT Univ., Melbourne, VIC, Australia
Abstract :
We propose and analyze an organization for a field-programmable gate array structure that operates using a balanced ternary logic system where the logic set {±1, 0} maps directly to equivalent voltage levels {±1.0V, 0.0V}. Circuits for basic components such as a ternary buffer, flip-flop and LUT are described based on the characteristics of a commercial silicon-on-sapphire process that offers multiple simultaneous transistor thresholds. A simple example of a balanced ternary FIR filter is mapped to the FPGA and some preliminary estimates made of its performance and area.
Keywords :
FIR filters; field programmable gate arrays; flip-flops; ternary logic; FIR filter; balanced ternary FPGA; balanced ternary logic system; field-programmable gate array; flip flop; silicon-on-sapphire process; ternary buffer; Adaptive filters; Arithmetic; CMOS logic circuits; Field programmable gate arrays; Finite impulse response filter; Flip-flops; Logic arrays; Multivalued logic; Table lookup; Voltage;
Conference_Titel :
Field-Programmable Technology, 2009. FPT 2009. International Conference on
Conference_Location :
Sydney, NSW
Print_ISBN :
978-1-4244-4375-8
Electronic_ISBN :
978-1-4244-4377-2
DOI :
10.1109/FPT.2009.5377659
