A precise ΔΣ-based Digitally Controlled Oscillator (DCO) for all-digital PLL

Author

Jafarzade, Samira ; Jannesari, Abumoslem

Author_Institution

Tarbiat Modares Univ., Tehran, Iran

fYear

2013

fDate

14-16 May 2013

Firstpage

1

Lastpage

4

Abstract

A Digitally Controlled Oscillator (DCO) for the frequency band of 1700-1900 MHz is presented. This architecture achieves a frequency resolution less than 1-kHz. The DCO is a part of an All-Digital Phase-Locked Loop (ADPLL) for GSM-1800 and GSM-900 applications implemented in a 0.18 μm CMOS process. In this architecture an 18-bit delta sigma digital to analog converter and a voltage controlled LC oscillator is used. The used ΔΣ DAC is a fourth order structure with 450 MHz sampling frequency, Over Sampling Ratio (OSR) =128 and 118 dB SNR. The bandwidth of this ΔΣ DAC is about 1.8 MHz. The phase noise of the presented DCO at 500 kHz offset frequency is -115 dBc/Hz.

Keywords

CMOS digital integrated circuits; UHF oscillators; delta-sigma modulation; digital phase locked loops; phase noise; voltage-controlled oscillators; CMOS process; DCO; GSM-1800; GSM-900; OSR; all-digital PLL; all-digital phase-locked loop; delta sigma digital to analog converter; fourth order structure; frequency 1700 MHz to 1900 MHz; frequency 450 MHz; frequency resolution; oversampling ratio; phase noise; precise ΔΣ-based digitally controlled oscillator; size 0.18 mum; voltage controlled LC oscillator; word length 18 bit; Phase locked loops; Phase noise; Solid state circuits; Tuning; Voltage-controlled oscillators; ΔΣ DAC; ADPLL; CMOS; DCO; LC oscillator;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering (ICEE), 2013 21st Iranian Conference on

Conference_Location

Mashhad

Type

conf

DOI

10.1109/IranianCEE.2013.6599744

Filename

6599744