Profile driven data-dependency analysis for improved high level language hardware synthesis

Existing high-level hardware synthesis tools typically focus on the automated discovery of opportunities for Instruction Level Parallelism (ILP) or alternatively allow designers to explicitly specify instances or opportunities for ILP. We present a novel profiling driven approach to the automated discovery of higher level speculative parallelism opportunities for custom-hardware implementations. The synthesis approach proposed here is to use the customisation capabilities of reconfigurable platforms to implement application specific speculative devices that capitalise on thread and loop level parallelism opportunities that occur with low (or zero) frequency data dependencies. In this paper our program profiling and partitioning techniques are detailed and analysis results are used to generate promising theoretical limits on speedups achievable through thread level parallelism. Such speedups are orthogonal to the gains achievable using existing ILP based optimisations. Our analysis and profiling tools are implemented within the Low Level Virtual Machine (LLVM) compiler infrastructure and results are generated from the SPEC2000INT benchmark suite.