DocumentCode :
3049516
Title :
Optimization of modular multiplication on FPGA using don´t care conditions
Author :
Alizadeh, Bijan ; Fujita, Masahiro
Author_Institution :
VLSI Design & Educ. Center (VDEC), Univ. of Tokyo & CREST, Tokyo, Japan
fYear :
2009
fDate :
9-11 Dec. 2009
Firstpage :
399
Lastpage :
402
Abstract :
In this paper we make use of don´t care conditions to propose a word-level Don´t-Care Optimization (DC-Opt) technique for modular multipliers by taking into account LUT-based FPGA architectures. This technique can easily be utilized for large arithmetic circuits and it can provide a superior implementation in terms of area compared to the state-of-the art optimizations. Experimental results show an average saving of 17% of area consumption compared to the conventional binary structures and residue number system (RNS) based multipliers on FPGA.
Keywords :
field programmable gate arrays; multiplying circuits; optimisation; residue number systems; LUT-based FPGA architectures; arithmetic circuits; binary structures; don´t care conditions; don´t care optimization; field programmable gate array; modular multiplication optimization; modular multipliers; residue number system; Application specific integrated circuits; Arithmetic; Art; Circuit synthesis; Design optimization; Digital signal processing; Field programmable gate arrays; Logic; Table lookup; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology, 2009. FPT 2009. International Conference on
Conference_Location :
Sydney, NSW
Print_ISBN :
978-1-4244-4375-8
Electronic_ISBN :
978-1-4244-4377-2
Type :
conf
DOI :
10.1109/FPT.2009.5377687
Filename :
5377687
Link To Document :
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