Detailed study of the time estimation in level-crossing analog-to-digital converters

Level-crossing analog-to-digital converters (LC-ADCs) have shown to be power-efficient for a wide range of applications where sparse signals are processed. In this paper, after addressing different timing schemes in LC-ADCs, a comprehensive analysis on the effect of main error sources on the LC-ADC performance is presented. Specifically, limited resolution of the timer, limited accuracy of the quantization levels and the comparator delay are studied as main error sources. Some design considerations and a more-accurate closed-form equation for the signal-to-noise ratio (SNR) are presented and confirmed using behavioral simulations.