Efficient delay-insensitive RSFQ circuits

It is reasonable to project that continuing progress in micro-electronics will lead to computing systems based on circuit elements with switching times on the order of a few picaseconds. Such speeds are likely beyond the capabilities of CMOS. One promising technology is Rapid Single Flux Quantum (RSFQ) circuits based on super-conducting Josephson junction devices. However, for such high-speed technologies, clock skew even over short distances can make synchronous circuit design prohibitively difficult. We have introduced a variant of delay insensitive (DI) asynchronous logic called conservative delay insensitive (CDI) logic which has particularly nice properties for use in RSFQ technology. Not only does it solve high-speed clocking problems, but its primitive elements appear to be more efficiently implementable in RSFQ technology than are traditional Boolean logic primitives and its property of minimizing the creation and destruction of signal pulses avoids some difficult implementation issues in RSFQ