Beyond test pattern generation: Coverage analysis

The size and complexity of the very large scale integrated circuits are ever increasing because of rapid advancements of deep-submicron and nanometer technologies. It has become imperative to address and attack the problems associated with verification at earlier design stages. The paper proposes a high level design verification scheme for the circuits designed at the behavioral level. The scheme is based on selection of a goal node in a control flow graph representation of a design under test. The scheme focuses on generation of suitable test patterns that adds gaining confidence in correctness of the design via code coverage metrics. The scheme does complete verification for a design in two attempts. First time verification attempts testing that exercises a set of test patterns to ensure the correctness. Second time verification involves code coverage analysis with the generated test patterns that accounts amount of correctness of the design. Experiments have been accomplished on a number of custom-built as well as ITC´99 benchmark circuits and establish the scalability of the proposed scheme. Experimental results establish the fact that high code coverage guarantees quality circuit design.