GaAs: Practical Interconnection Design Considerations

The transition from silicon technology to GaAs brings with it almost an order of magnitude increase in device rise and fall times. These edge rates promise to increase even further as HEMT (High Electron Mobility Transistor) devices mature. Presently, proper high-speed TTL design requires transmission line analysis techniques but the interconnection constraints imposed by GaAs are considerably more stringent. This paper will address these interconnection issues from a practical design standpoint. It will include printed circuit layout considerations, choosing circuit board materials, maintaining signal integrity, power distribution considerations and interfacing with other logic families.