An efficient DELOTS Algorithm for low leakage current at nano-scale transistor

The current switching from μ-technology to n-technology generated a new challenges for CMOS circuit design. The optimization of power and delay together becomes the main issue in CMOS circuits design. Based on transistor level, a new algorithm for optimizing the Power Delay Product (PDP) for digital CMOS circuits is proposed in this paper. This algorithm is composed of three models: Graph Model (GM), Mathematical Model (MM) and Heuristic Model (HM). These Models work homogeneously to enhance the circuit performance (Delay) and reduce the circuit power dissipation (leakage) by selecting the optimal width size for each transistor in the circuit. All the measurements and simulation results of the new approach have been performed under 22nm BSIM4 Foundries. The average improvement in PDP was 31% for Full Adder circuit of 24 transistors and 43% for C17 ISIAC benchmark.