A hardware digital processor for image bandwidth compression

The paper describes a feasibility study of a digital two-dimensional transformer which is the main processing part of a real-time, hybrid coder for transmission of television signals. The spatial transform algorithm is separated into one-dimensional transforms and is hardware implemented with two pipelined chains of arithmetical elements. The chain elements, which operate on bitserial data, are single chip structures based on custom-designed NMOS technology. Design steps including system organization, processor architecture and hardware realization are discussed. The proposed real-time image processor has an efficient hardware utilization with relaxed complexity as compared with conventional architectural designs.