System partitioning for multi-chip modules under timing and capacity constraints

The authors propose an efficient and effective algorithm for system partitioning under timing and capacity constraints. They consider the problem of assigning functional blocks into slots on multi-chip modules in high-level design to have fast feedback on the impact of high-level design decisions. A clustering step is used to ensure timing correctness, followed by packing and the K&L algorithm to satisfy capacity constraints while minimizing net crossings. The method is unique in that net crossings are minimized, while satisfying timing and capacity constraints. Test results showed that the method eliminated timing violations and obtained a comparable number of net crossings to that of the algorithm proposed by C.M. Fiduccia and R.M. Mattheyses (1982) with a similar run time. The method can be extended to use partitioning algorithms other than that of Fiduccia and Mattheyses