Exploring FPGA technology mapping for fracturable LUT minimization

Modern commercial Field-Programmable Gate Array (FPGA) architectures contain look-up-tables (LUTs) that can be “fractured” into two smaller LUTs. The potential of packing two LUTs into a space that could accommodate only one in traditional architectures complicates technology mapping´s LUT minimization objective. Previous works introduced edge-recovery techniques and the concept of LUT balancing, both of which produce mappings that pack into fewer fracturable LUTs. We combine these two ideas and evaluate their effectiveness for one commercial and four academic FPGA architectures, all of which contain fracturable LUTs. When used in conjunction, edge-recovery and LUT balancing yield a 8.9% to 16.2% reduction in fracturable LUT use, depending upon architectural constraints.