Title :
Manufacturable and reliable spin-on-glass planarization process for 1 mu m CMOS double layer metal technology
Author :
Morimoto, Seiichi ; Grant, Sarah Queller
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
A spin-on-glass (SOG) etchback process has been used to planarize the intermetal dielectric film in small-geometry devices. The major aspects of SOG planarization including process integration, SOG material characteristics, and manufacturability and reliability issues are reviewed. Planarity of less than 45 degrees is obtained by SOG spin followed by etchback with a SOG/CVD selectivity of one to one. An organic-type SOG was shown to fill a 1- mu m minimum metal-1 space without cracking. Packaged parts have been tested under an accelerated temperature and humidity ambient, and the SOG was shown to be reliable.<>
Keywords :
CMOS integrated circuits; integrated circuit technology; life testing; metallisation; reliability; sputter etching; 1 micron; CMOS double layer metal technology; SOG etchback process; SOG/CVD selectivity; accelerated testing; intermetal dielectric film; manufacturability; process integration; reliability; small-geometry devices; spin-on-glass planarization; Dielectric films; Dielectric materials; Etching; Life estimation; Manufacturing processes; Materials reliability; Packaging; Planarization; Temperature; Testing;
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1988. Proceedings., Fifth International IEEE
Conference_Location :
Santa Clara, CA, USA
DOI :
10.1109/VMIC.1988.14220
