Title :
Transient device simulation of trap-assisted leakage in non-volatile memory cell
Author :
Watanabe, Hiroshi
Author_Institution :
Adv. LSI Technol. Labs., Toshiba Corp., Yokohama
Abstract :
In order to study how a local trap degrades data retention characteristics of floating gate nonvolatile memory cell, a general-purpose Single-Electron Device Simulator (SEDS) developed for Si-dot is improved to carry out a very wide range transient analysis from 0.1 pico-seconds to 10 years. As a result, it is found that the data retention is degraded by the direct tunneling enhanced due to positive charge stored at the trap inside the inter-poly dielectric but not by trap-assisted tunneling.
Keywords :
elemental semiconductors; random-access storage; silicon; single electron devices; tunnelling; Si; data retention; floating gate nonvolatile memory cell; inter-poly dielectric; single-electron device simulator; transient device simulation; trap-assisted leakage; tunneling; Analytical models; Capacitance; Character generation; Degradation; Electron emission; Electron traps; Nonvolatile memory; Single electron devices; Transient analysis; Tunneling; device-simulation; local trap; nonvolatile memory; transient analysis;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2008. SISPAD 2008. International Conference on
Conference_Location :
Hakone
Print_ISBN :
978-1-4244-1753-7
DOI :
10.1109/SISPAD.2008.4648233
