Modeling the VTH fluctuations in nanoscale Floating Gate memories

Author

Calderoni, A. ; Fantini, P. ; Ghetti, A. ; Marmiroli, A.

Author_Institution

R&D - Technol. Dev., Numonyx, Agrate Brianza

fYear

2008

fDate

9-11 Sept. 2008

Firstpage

49

Lastpage

52

Abstract

Tight bits distribution is a must to fabricate multi-level Non-Volatile Memory (NVM) technology needed to reach a high degree of integration. On the contrary, the Non-Volatile cell shrink to nanoscale sizes produces a huge modulation in the device performances when atomistic scale fluctuations occur. The present work provides a new physically-based model allowing describing, through a simple analytical approach, the statistical V_TH spread for Floating Gate based NVM technologies with nanoscale dimensions.

Keywords

integrated circuit modelling; random-access storage; VTH fluctuations modelling; atomistic scale fluctuations; nanoscale floating gate memories; non-volatile memory technology; tight bits distribution; Current measurement; Flash memory; Fluctuations; Nanoscale devices; Nonvolatile memory; Research and development; Semiconductor device measurement; Signal to noise ratio; Statistical distributions; Threshold voltage; Fluctuations; Modeling; Noise; Non-Volatile Memory; Statistical distribution;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2008. SISPAD 2008. International Conference on

Conference_Location

Hakone

Print_ISBN

978-1-4244-1753-7

Type

conf

DOI

10.1109/SISPAD.2008.4648234

Filename

4648234