DocumentCode
3053238
Title
Setting test conditions for improving SRAM reliability
Author
Fonseca, R. Alves ; Dilillo, L. ; Bosio, A. ; Girard, P. ; Pravossoudovitch, S. ; Virazel, A. ; Badereddine, N.
Author_Institution
LIRMM, Univ. de Montpellier II, Montpellier, France
fYear
2010
fDate
24-28 May 2010
Firstpage
257
Lastpage
257
Abstract
In the context of SRAM testing, we propose a methodology to define proper conditions under which SRAMs should be tested to improve their reliability. This methodology is especially suitable to deal with the impact of threshold voltage variability affecting SRAM core-cell transistors. By establishing an objective manner of comparing different test conditions, the proposed study shows how it is possible to detect SRAM core-cells with poor quality by applying a reduced set of test runs. The proposed methodology also allows determining the most appropriate DfT (Design-for-Test) technique for each peculiar SRAM design and technology.
Keywords
SRAM chips; integrated circuit reliability; integrated circuit testing; SRAM core-cell transistors; SRAM reliability; SRAM testing; design-for-test technique; threshold voltage variability; Design for testability; Measurement; Performance evaluation; Pulsed power supplies; Random access memory; Space vector pulse width modulation; Stress; Temperature; Testing; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium (ETS), 2010 15th IEEE European
Conference_Location
Praha
ISSN
1530-1877
Print_ISBN
978-1-4244-5834-9
Electronic_ISBN
1530-1877
Type
conf
DOI
10.1109/ETSYM.2010.5512734
Filename
5512734
Link To Document