Level shifts and gate interfaces as vital ingredients in modeling of charge trapping

We present a detailed modeling study of charging and discharging traps in dielectrics used in modern semiconductor devices. Existing descriptions of charge trapping are often restricted to charge injection from the substrate and ignore the presence of the gate contact as a source/sink of charge carriers. This assumption loses its justification when the gate dielectric shrinks into the nanometer range. Furthermore, a novel picture of tunneling into and out of defects has emerged from first principles calculations which questions the conventional concept of fixed trap levels irrespective of their charge state. Consequently, focus is put on the development of a novel rigorous model merging both effects into one general description of charge trapping.