DocumentCode
3053286
Title
A shared BIST optimization methodology for memory test
Author
Zaourar, Lilia ; Chentoufi, Jihane Alami ; Kieffer, Yann ; Wenzel, Amaud ; Grandvaux, Frederic
Author_Institution
G-SCOP Lab., Grenoble INP, Grenoble, France
fYear
2010
fDate
24-28 May 2010
Firstpage
255
Lastpage
255
Abstract
We present a methodology, based on genetic algorithms, that optimizes shared heterogeneous Memory BIST architectures with regards to area, testing peak power and test time.
Keywords
built-in self test; genetic algorithms; memory architecture; BIST optimization methodology; built-in self test; genetic algorithm; memory test; shared heterogeneous memory BIST architecture; test time; testing peak power; Built-in self-test; Decision support systems; Optimization methods; Testing; Virtual reality; Bist; memory; optimization; sharing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium (ETS), 2010 15th IEEE European
Conference_Location
Praha
ISSN
1530-1877
Print_ISBN
978-1-4244-5834-9
Electronic_ISBN
1530-1877
Type
conf
DOI
10.1109/ETSYM.2010.5512736
Filename
5512736
Link To Document