DocumentCode
3053325
Title
RT level power analysis
Author
Zhu, Jianwen ; Agrawal, Poonam ; Gajski, Daniel D.
Author_Institution
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
fYear
1997
fDate
28-31 Jan 1997
Firstpage
517
Lastpage
522
Abstract
Elevating power estimation to architectural and behavioral level is essential for design exploration beyond logic level. In contrast with purely statistical approach, an analytical model is presented to estimate the power consumption in datapath and controller for a given RT level design. Experimental result shows that order of magnitude speed-up over low level tools as well as satisfactory accuracy can be achieved. This work can also serve as the basis for behavioral level estimation tool
Keywords
circuit layout CAD; high level synthesis; logic CAD; RT level power analysis; analytical model; architectural level; behavioral level; behavioral level estimation tool; controller; design exploration; logic level; power estimation; statistical approach; Capacitance; Clocks; Computer science; Energy consumption; Integrated circuit interconnections; Libraries; Power dissipation; Semiconductor device modeling; Statistics; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location
Chiba
Print_ISBN
0-7803-3662-3
Type
conf
DOI
10.1109/ASPDAC.1997.600323
Filename
600323
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