ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration

Dynamic Partial Reconfiguration (DPR) enables software-like flexibility in hardware designs by allowing some of the logic on a Field Programmable Gate Array (FPGA) to be reconfigured while the rest continues to operate. However, such flexibility introduces challenges for verifying DPR design functionality because there is no straightforward way to simulate DPR at Register Transfer Level (RTL). This paper proposes the ReSim library to enable the RTL simulation of DPR. The library uses a simulation-only layer to hide the physically dependent details of DPR designs while providing sufficient accuracy for functional verification. The library is extensible and reusable. We assess the feasibility and demonstrate the value of our tool via two case studies of DPR designs.