DocumentCode :
3053539
Title :
Reconfigurable Concurrent Error Detection adaptive to dynamicity of power constraints
Author :
Almukhaizim, Sobeeh ; Bunian, Sara ; Sinanoglu, Ozgur
Author_Institution :
Comput. Eng. Dept., Kuwait Univ., Safat, Kuwait
fYear :
2010
fDate :
24-28 May 2010
Firstpage :
248
Lastpage :
248
Abstract :
In this preliminary study, we evaluate a reconfigurable low-power duplication-based Concurrent Error Detection (CED) infrastructure for logic circuits. The key idea is to enable/disable the operation of the duplicate circuit, resulting in the retention of the input values to the duplicate circuit (i.e., reduction in power dissipation) at the cost of some reduction in CED coverage. The results indicate that power dissipation is commensurate with CED coverage, motivating the use of LFSR structures to easily generate and reconfigure conditions, enabling their dynamic adjustment to adapt to the power constraints of the system.
Keywords :
logic circuits; low-power electronics; reconfigurable architectures; logic circuits; power constraints; power dissipation; reconfigurable concurrent error detection; reconfigurable low-power duplication; CMOS technology; Circuits; Computer errors; Concurrent computing; Costs; Drives; Multiplexing; Power dissipation; Power engineering computing; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ETS), 2010 15th IEEE European
Conference_Location :
Praha
ISSN :
1530-1877
Print_ISBN :
978-1-4244-5834-9
Electronic_ISBN :
1530-1877
Type :
conf
DOI :
10.1109/ETSYM.2010.5512745
Filename :
5512745
Link To Document :
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