DocumentCode :
3053608
Title :
New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism
Author :
Zhang, Xiao ; Kerkhoff, Hans G. ; Vermeulen, Bart
Author_Institution :
Centre of Telecommun. & Inf. Technol. (CTIT), Univ. of Twente, Enschede, Netherlands
fYear :
2010
fDate :
24-28 May 2010
Firstpage :
243
Lastpage :
243
Abstract :
Recent advances in the semiconductor industry enable the integration of many processing units on a single die and new processors are often included into large many-core SoCs. The dependability of such a many-core processor is essential for many mission-critical applications. Ideas such as the Know-Good-Tile concept [1] or majority-voting among tiles [2] have been proposed to explore the possibility to enhance the dependability of a many-core processor.
Keywords :
integrated circuit testing; NoC; dependable many core processor; know good tile concept; mission critical application; network-on-chip; scan based test strategy; semiconductor industry; test access mechanism; Array signal processing; Bandwidth; Network-on-a-chip; Performance evaluation; Resumes; Semiconductor device testing; Switches; System testing; Tiles; USA Councils;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ETS), 2010 15th IEEE European
Conference_Location :
Praha
ISSN :
1530-1877
Print_ISBN :
978-1-4244-5834-9
Electronic_ISBN :
1530-1877
Type :
conf
DOI :
10.1109/ETSYM.2010.5512748
Filename :
5512748
Link To Document :
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