Scan based speed-path debug for a microprocessor

Speedpath debug is a critical step in improving clock frequency of a design to meet the performance requirement. However, speedpath debug based on functional patterns can be very expensive. In this paper, we explore scan-based speedpath debug techniques based on at-speed scan test patterns. Several enhancements are implemented to improve over an earlier proposed scan-based speedpath diagnosis algorithm. We further report the application results by applying the improved algorithm to a leading-edge high performance microprocessor design.